Time alignment in the prior art consists mainly of oversampling the signals of the forward and feedback path and then applying the cross correlation techniques in order to determine the delay with high accuracy between the two signals. Other techniques are based on some type of time delay estimator (TDE) in a closed loop fashion, however not all TDEs will work and produce a high accuracy useful time alignment.
The techniques may be found in the following patents and technical papers. These references are hereby incorporated into the present disclosure as if fully set forth herein:
REF1—U.S. Patent Application Publication No. 2003-0072388 A1 to Francos, et al., entitled “Time Delay Estimator In A Transmitter”;
REF2—U.S. Patent Application Publication No. 2001-0005402 to Nagatani, et al., entitled “Distortion Compensating Apparatus”;
REF3—U.S. Patent Application Publication No. 2008-0205571 to Muhammad, et al., entitled “System And Method For Time Aligning Signals In Transmitters”;
REF4—Feipeng Wang et al., “Design Of Wide-Bandwidth Envelope Tracking Power Amplifiers For OFDM Applications”, IEEE Transactions On Microwave Theory And Techniques, vol. 53, no. 4, April 2005;
Nagata, Y., “Linear Amplification Technique For Digital Mobile Communications”, Vehicular Technology Conference, 1989 IEEE 39th; 1-3 May 1989, pp. 159-164, Volume 1; and
Hao Li and al., “A Fast Digital Predistortion Algorithm For Radio-Frequency Power Amplifier Linearization With Loop Delay Compensation”, IEEE Journal Of Selected Topics In Signal Processing, Volume 3, No. 3, June 2009.
The techniques based on oversampling the signals in the prior arts have limitations. In order to achieve high accuracy of time alignment, the acquired reference and feedback signals must be oversampled. The high sampling rate is required before the cross correlation operation to increase the accuracy of time alignment. Ten to twenty times oversampling is common and this requires a large amount of computation to perform the oversampling and the cross-correlation operations, and a large amount of information on the feedback signal is needed to achieve high accuracy in time alignment; therefore, a costly powerful DSP processor is needed. This becomes impractical from the point of view of implementation, cost, and speed of time aligning.
Also, it is very difficult to implement the scheme of oversampling the signal followed by a cross correlation operation in a Field-Programmable Gate Array (FPGA) due to the limitation of the FPGA clock speed; therefore, these techniques do not support real-time tracking of the time delay in order to make the proper delay adjustment.
A TDE block can be used to estimate the time shift between two signals. To perform the estimation, the TDE uses a correlation algorithm. However, the techniques of computing the correlation algorithm in the prior arts have limitations. That is, not all TDE blocks are useful in a DPD system. Some of the designs do not have the proper computational accuracy because they try to compute the correlation between two signals by representing the signals using one bit instead of representing the digital signals with multibit. Regarding the variable delay blocks, there are many ways to implement them. However, in the context of DPDs, it is important to use a variable delay block with a wide and flat bandwidth. In addition, TDEs that have been used previously do not support the dual time alignment needed for envelope elimination and restoration and envelope tracking (EER/ET) systems.